Part Number Hot Search : 
43860 R5F2128 MC600 4LS126 TPS80 2SC2623 MAX1501 AKD45
Product Description
Full Text Search
 

To Download ISLA110P50 Datasheet File
  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
　
 

  Datasheet File OCR Text:
  fn7606 rev 2.00 page 1 of 34 july 25, 2011 fn7606 rev 2.00 july 25, 2011 ISLA110P50 10-bit, 500msps a/d converter datasheet the ISLA110P50 is a low-power, high-performance, 500msps analog-to-digital converter design ed with intersil?s proprietary femtocharge ? technology on a standard cmos process. the ISLA110P50 is part of a pin-comp atible portfolio of 8, 10 and 12-bit a/ds. this device is an upgrade of the kad551xp-50 product family and is pin similar. the device utilizes two time-interleaved 250msps unit a/ds to achieve the ultimate sample rate of 500msps. a single 500mhz conversion clock is presented to the converter, and all interleave clocking is managed internally. the proprietary intersil interleave engine (i2e) performs automatic fine correction of offset, gain, and sample time skew mismatches between the unit a/ds to optimize performance. no external interleaving algorithm is required. a serial peripheral interface (spi) port allows for extensive configurability of the a/d. the sp i also controls the interleave correction circuitry, allowing the system to issue continuous calibration commands as well as configure many dynamic parameters. digital output data is presented in selectable lvds or cmos formats. the ISLA110P50 is available in a 72 ld qfn package with an exposed paddle. performance is specified over the full industrial temperature range (-40c to +85c). features ? 1.15ghz analog input bandwidth ? 90fs clock jitter ? automatic fine interleave correction calibration ? multiple chip time alignmen t support via the synchronous clock divider reset ? programmable gain, offset and skew control ?over-range indicator ? clock phase selection ? nap and sleep modes ? two?s complement, gray code or binary data format ? ddr lvds-compatible or lvcmos outputs ? programmable test patterns and internal temperature sensor applications ? radar and electronic/signal intelligence ? broadband communications ? high-performance data acquisition key specifications ?snr = 60.6dbfs for f in = 190mhz (-1dbfs) ? sfdr = 80dbc for f in = 190mhz (-1dbfs) ? total power consumption = 441mw sha 1.25v vinp vinn 10- bit 250msps adc clock management sha -bit 250msps adc clkp clkn spi control vref clkoutp clkoutn orp orn outfmt outmode + C vcm vref i2e gain/ offset/skew adjustments clkdivrstp clkdivrstn d[9:0]p d[9:0]n avdd ovdd 10 digital error correction ognd sdo sdio sclk csb agnd napslp resetn figure 1. block diagram pin-compatible family model resolution speed (msps) isla112p50 12 500 ISLA110P50 10 500 isla118p50 8 500
ISLA110P50 fn7606 rev 2.00 page 2 of 34 july 25, 2011 table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 switching specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . 10 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power-on calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 user initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 over-range indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 nap/sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 i2e requirements and restrictions . . . . . . . . . . . . . . . . . 18 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 active run state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 notch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 nyquist zones. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 configurability and communication . . . . . . . . . . . . . . . . . . . . 19 clock divider synchronous reset . . . . . . . . . . . . . . . . . . . . 20 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . 22 spi physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 indexed device configuration/control. . . . . . . . . . . . . . . . . . 23 ac rms power threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 address 0x60-0x64: i2e initialization . . . . . . . . . . . . . . . . . . 25 device test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 spi memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 a/d evaluation platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 split ground and power planes . . . . . . . . . . . . . . . . . . . . . . . 31 clock input considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 exposed paddle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 bypass and filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 lvds outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 lvcmos outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 unused inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ISLA110P50 fn7606 rev 2.00 page 3 of 34 july 25, 2011 pin configuration ISLA110P50 (72 ld qfn) top view ordering information part number (notes 1, 2) part marking speed (msps) temp. range (c) package (pb-free) pkg. dwg. # ISLA110P50irz ISLA110P50 irz 500 -40 to +85 72 ld qfn l72.10x10c notes: 1. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. for moisture sensitivity level (msl), please see device information page for ISLA110P50 . for more information on msl please see techbrief tb363 . figure 2. pin configuration r n f i d e n t i a l i n f o r m a t i o n 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 avdd clkp outmode napslp avdd resetn clkn ovss ovdd clkdivrstp clkdivrstn dnc dnc dnc dnc dnc dnc ovdd avdd outfmt sdio sclk csb sdo ovss orp orn d9p d9n d8p d8n d7p d7n ovdd ovss avss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 clkoutp clkoutn d6p d6n d5p d5n d4p d4n ovss d3p d3n d2p d2n d1p d1n d0p d0n rlvds avdd dnc dnc avdd avss avss vinn vinp avss avdd dnc dnc vcm dnc dnc res res connect thermal pad to avss dnc pd
ISLA110P50 fn7606 rev 2.00 page 4 of 34 july 25, 2011 pin descriptions pin number lvds [lvcmos] na me lvds [lvcmos] function 1, 6, 12, 19, 24, 71 avdd 1.8v analog supply 2, 5, 13, 14, 16, 17, 18, 30, 31, 32, 33, 34, 35 dnc do not connect 3, 4 res reserved. (4.7k ? pull-up to ovdd is required for each of these pins) 7, 8, 11, 72 avss analog ground 9, 10 vinn, vinp analog input negative, positive 15 vcm common mode output 20, 21 clkp, clkn clock input true, complement 22 outmode tri-level output mode (lvds, lvcmos) 23 napslp tri-level power control (nap, sleep modes) 25 resetn power-on reset (active low) 26, 45, 55, 65 ovss output ground 27, 36, 56 ovdd 1.8v output supply 28, 29 clkdivrstp, clkdivrstn sample clock synchronous divider reset positive, negative 37, 38 d0n, d0p [nc, d0] lvds bit 0 output complement, true [nc, lvcmos bit 0] 39, 40 d1n, d1p [nc, d1] lvds bit 1 output complement, true [nc, lvcmos bit 1] 41, 42 d2n, d2p [nc, d2] lvds bit 2 output complement, true [nc, lvcmos bit 2] 43, 44 d3n, d3p [nc, d3] lvds bit 3 output complement, true [nc, lvcmos bit 3] 46 rlvds lvds bias resistor (connect to ovss with a 10k ? , 1% resistor) 47, 48 clkoutn, clkoutp [nc, clkout] lvds clock output complement, true [nc, lvcmos clkout] 49, 50 d4n, d4p [nc, d4] lvds bit 4 output complement, true [nc, lvcmos bit 4] 51, 52 d5n, d5p [nc, d5] lvds bit 5 output complement, true [nc, lvcmos bit 5] 53, 54 d6n, d6p [nc, d6] lvds bit 6 output complement, true [nc, lvcmos bit 6] 57, 58 d7n, d7p [nc, d7] lvds bit 7 output complement, true [nc, lvcmos bit 7] 59, 60 d8n, d8p [nc, d8] lvds bit 8 output complement, true [nc, lvcmos bit 8] 61, 62 d9n, d9p [nc, d9] lvds bit 9 (msb) output complement, true [nc, lvcmos bit 9] 63, 64 orn, orp [nc, or] lvds over-range co mplement, true [nc, lvcmos over-range] 66 sdo spi serial data output (4.7k ? pull-up to ovdd is required) 67 csb spi chip select (active low) 68 sclk spi clock 69 sdio spi serial data input/output 70 outfmt tri-level output data format (two?s comp., gray code, offset binary) pd avss exposed paddle. analog ground note: lvcmos output mode functionality is shown in brackets (nc = no connection)
ISLA110P50 fn7606 rev 2.00 page 5 of 34 july 25, 2011 absolute maximum rating s thermal information avdd to avss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4v to 2.1v ovdd to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4v to 2.1v avss to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v analog inputs to avss . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to avdd + 0.3v clock inputs to avss . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to avdd + 0.3v logic input to avss . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to ovdd + 0.3v logic inputs to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to ovdd + 0.3v thermal resistance (typical) ? ja (c/w) ? jc (c/w) 72 ld qfn (notes 3, 4, 5) . . . . . . . . . . . . . . 23 0.75 operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp notes: 3. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 4. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 5. for solder stencil layout and reflow guidelines, please see tech brief tb389 . caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), a in = -1dbfs, f in = 105mhz, f sample = 500msps, after completion of i2e calibration. parameter symbol conditions ISLA110P50 (note 6) units min typ max dc specifications (note 6) analog input full-scale analog input range v fs differential 1.41 1.45 1.52 v p-p input resistance r in differential 500 ? input capacitance c in differential 1.9 pf full scale range temp. drift a vtc full temp 325 ppm/c input offset voltage v os -10 2.0 10 mv gain error e g 2.0 % common-mode output voltage v cm 435 535 635 mv clock inputs inputs common mode voltage 0.9 v clkp, clkn input swing 0.2 1.8 v power requirements 1.8v analog supply voltage avdd 1.7 1.8 1.9 v 1.8v digital supply voltage ovdd 1.7 1.8 1.9 v 1.8v analog supply current iavdd 173 186 ma 1.8v digital supply current (note 7) i ovdd 3ma lvds, i2e powered down, notch filter powered down 79 86 ma 3ma lvds, i2e on, notch filter on 124 ma power supply rejection ratio psrr 30mhz, 200mv p-p -36 db total power dissipation normal mode p d 2ma lvds, i2e powered down, notch filter powered down 441 mw 3ma lvds, i2e powered down, notch filter powered down 454 490 mw 3ma lvds, i2e on, notch filter powered down 520 mw 3ma lvds, i2e on, notch filter on 535 mw nap mode p d 164 179 mw
ISLA110P50 fn7606 rev 2.00 page 6 of 34 july 25, 2011 sleep mode p d 28 34 mw nap mode wakeup time (note 8) sample clock running 2.75 s sleep mode wakeup time (note 8) sample clock running 1 ms ac specifications (note 9) differential nonlinearity dnl -0.35 0.15 0.35 lsb integral nonlinearity inl -0.5 0.2 0.5 lsb minimum conversion rate (note 10) f s min 80 msps maximum conversion rate f s max 500 msps signal-to-noise ratio (notes 11, 12) snr f in = 10mhz 60.7 dbfs f in = 105mhz 59.9 60.7 dbfs f in = 190mhz 60.6 dbfs f in = 364mhz 60.3 dbfs f in = 495mhz 60.1 dbfs f in = 605mhz 59.7 dbfs f in = 995mhz 58.6 dbfs signal-to-noise and distortion (notes 11, 12) sinad f in = 10mhz 60.7 dbfs f in = 105mhz 59.8 60.7 dbfs f in = 190mhz 60.5 dbfs f in = 364mhz 60.0 dbfs f in = 495mhz 59.4 dbfs f in = 605mhz 57.9 dbfs f in = 995mhz 48.2 dbfs effective number of bits (notes 11, 12) enob f in = 10mhz 9.79 bits f in = 105mhz 9.60 9.79 bits f in = 190mhz 9.77 bits f in = 364mhz 9.68 bits f in = 495mhz 9.58 bits f in = 605mhz 9.33 bits f in = 995mhz 7.71 bits spurious-free dynamic range (notes 11, 12) sfdr f in = 10mhz 84 dbc f in = 105mhz 70 86 dbc f in = 190mhz 80 dbc f in = 364mhz 74 dbc f in = 495mhz 68 dbc f in = 605mhz 63 dbc f in = 995mhz 48 dbc intermodulation distortion imd f in = 70mhz 89 dbc f in = 170mhz 87 dbc word error rate wer 10 -12 full power bandwidth fpbw 1.15 ghz electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), a in = -1dbfs, f in = 105mhz, f sample = 500msps, after completion of i2e calibration. (continued) parameter symbol conditions ISLA110P50 (note 6) units min typ max
ISLA110P50 fn7606 rev 2.00 page 7 of 34 july 25, 2011 i2e specifications offset mismatch-induced spurious power no i2e calibration performed -70 dbfs active run state enabled -81 dbfs i2e settling times i2epost_t calibration settling time for active run state 1000 ms minimum duration of valid analog input (note 13) t te allow one i2e iteration of offset, gain and phase correction 500 s largest interleave spur f in = 10mhz to 240mhz, active run state enabled, in track mode -94 dbc f in = 10mhz to 240mhz, active run state enabled and previously settled, in hold mode -82 dbc f in = 260mhz to 490mhz, active run state enabled, in track mode -89 dbc f in = 260mhz to 490mhz, active run state enabled and previously settled, in hold mode -79 dbc total interleave spurious power active run state enabled, in track mode, f in is a broadband signal in the 1 st nyquist zone -90 dbc active run state enabled, in track mode, f in is a broadband signal in the 2 nd nyquist zone -85 dbc sample time mismatch between unit a/ds active run state enabled, in track mode 30 fs gain mismatch between unit a/ds 0.01 % offset mismatch between unit a/ds 1mv notes: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 7. digital supply current is dependent upon the capacitive loading of the digital outputs. i ovdd specifications apply for 10pf load on each digital output. 8. see ?nap/sleep? for more detail. 9. ac specifications apply after internal calibration of the a/d is invoked at the given sample rate and temperature. refer to ? power-on calibration? and ?user initiated reset? for more detail. 10. the dll range setting must be changed for low speed operation. 11. the offset mismatch-induced spur energy, which occurs at f sample /2, is not included in any specification unless otherwise noted. 12. this specification only applies when i2e is in active run state, and in track mode. 13. limits are specified over the full operating temperature and voltage range and are established by characterization and not p roduction tested. electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), a in = -1dbfs, f in = 105mhz, f sample = 500msps, after completion of i2e calibration. (continued) parameter symbol conditions ISLA110P50 (note 6) units min typ max digital specifications parameter symbol conditions min typ max units cmos inputs input current high (sdio, resetn, csb, sclk) i ih v in = 1.8v 0 1 10 a input current low (sdio, resetn, csb, sclk) i il v in = 0v -25 -12 -5 a input voltage high (sdio, resetn, csb, sclk) v ih 1.17 v input voltage low (sdio, resetn, csb, sclk) v il 0.63 v
ISLA110P50 fn7606 rev 2.00 page 8 of 34 july 25, 2011 input current high (outmode, napslp, outfmt) (note 14) i ih 15 25 40 a input current low (outmode, napslp, outfmt) i il -4025-15a input capacitance c di 3pf lvds inputs (clkdivrstp, clkdivrstn) input common mode range v icm 825 1575 mv input differential swing (peak to peak, single ended) v id 250 450 mv input pull-up and pull-down resistance r ipu 1m ? lvds outputs differential output voltage (note 15) v t 3ma mode 620 mv p-p output offset voltage v os_lvds 3ma mode 950 965 980 mv output rise time t r 625 ps output fall time t f 625 ps cmos outputs voltage output high v oh i oh = -500a ovdd - 0.3 ovdd - 0.1 v voltage output low v ol i ol = 1ma 0.1 0.3 v output rise time t r 2ns output fall time t f 2ns digital specifications (continued) parameter symbol conditions min typ max units timing diagrams figure 3. lvds timing diagram figure 4. cmos timing diagram inp inn clkp clkn clkoutp clkoutn t a t cpd t dc t pd data n-l latency = l cycles sample n data n data n-l+1 data n-l+2 d[9:0]p d[9:0]n inp inn clkp clkn t a t cpd t dc t pd latency = l cycles sample n clkoutp clkoutn data n-l data n data n-l+1 data n-l+2 d[9:0]p d[9:0]n
ISLA110P50 fn7606 rev 2.00 page 9 of 34 july 25, 2011 switching specifications parameter condition symbol min typ max units a/d output aperture delay t a 375 ps rms aperture jitter j a 90 fs input clock to output clock propagation delay avdd, ovdd = 1.8v, t a = +25c t cpd 2.6 2.9 3.3 ns avdd, ovdd = 1.7v to 1.9v, t a = -40c to +85c t cpd 2.0 2.6 3.6 ns relative input clock to output clock propagation delay matching (note 16) avdd, ovdd = 1.7v to 1.9v, t a = -40c to +85c dt cpd -450 450 ps input clock to data propagation delay, lvds mode t pd 1.74 2.6 3.83 ns output clock to data propagation delay (note 13) lvds or cmos mode t dc -250 0 250 ps synchronous clock divider reset setup time (with respect to the positive edge of clkp) t rsts 300 75 ps synchronous clock divider reset hold time (with respect to the positive edge of clkp) t rsth 450 150 ps synchronous clock divider reset recovery time dll recovery time after synchronous reset t rstrt 52 s latency (pipeline delay) (note 17) l 17 cycles overvoltage recovery t ovr 1cycles spi interface (notes 18, 19) sclk period write operation t clk 32 cycles (note 18) read operation t clk 132 cycles csb ?? to sclk ? setup time read or write t s 2cycles csb ?? after sclk ? hold time read or write t h 11 cycles data valid to sclk ? setup time write t dsw 2cycles data valid after sclk ? hold time write t dhw 8cycles data valid after sclk ? time read t dvr 33 cycles data invalid after sclk ? time read t dhr 6cycles sleep mode csb ?? to sclk ? setup time (note 20) read or write in sleep mode t s 150 s notes: 14. the tri-level inputs internal switching thresholds are approximately 0.43v and 1.34v . it is advised to float the inputs, tie to ground or avdd depending on desired function. 15. the voltage is expressed in peak-to-peak differential swing. the peak-to-peak singled-ended swing is 1/2 of the differential swing. 16. the relative propagation delay is the timing of the output cl ock of any a/d with respect to the nominal timing of any other a/d, given that all devices are clocked at the same time and are matched in temperature and voltage. it is specified over the full operating temperature an d voltage range, and is established by characterization and not production tested. 17. the pipeline latency of this converter is fixed. 18. spi interface timing is directly proportional to the a/d sample period (t sample ). 19. the spi may operate asynchronously wi th respect to the a/d sample clock. 20. the csb setup time increases in sleep mode due to the reduced po wer state, csb setup time in nap mode is equal to normal mod e csb setup time (4ns min).
ISLA110P50 fn7606 rev 2.00 page 10 of 34 july 25, 2011 typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = 500msps. figure 5. snr and sfdr vs f in figure 6. hd2 and hd3 vs f in figure 7. snr and sfdr vs a in figure 8. hd2 and hd3 vs a in figure 9. snr and sfdr vs f sample figure 10. hd2 and hd3 vs f sample 40 45 50 55 60 65 70 75 80 85 90 0m 200m 400m 600m 800m 1g input frequency (hz) snr (dbfs) and sfdr (dbc) sfdr snr -100 -90 -80 -70 -60 -50 -40 0m 200m 400m 600m 800m 1g input frequency (hz) harmonic magnitude (dbc) hd3 hd2 20 30 40 50 60 70 80 90 100 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 input amplitude (dbfs) snr and sfdr sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) -110 -100 -90 -80 -70 -60 -50 -40 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 input amplitude (dbfs) snr and sfdr hd3 (dbfs) hd2 (dbfs) hd3 (dbc) hd2 (dbc) sfdr 50 55 60 65 70 75 80 85 90 95 250 300 350 400 450 500 sample rate (msps) snr (dbfs) and sfdr (dbc) snr 40 50 60 70 80 90 100 250 300 350 400 450 500 sample rate (msps) dbc hd3 hd2
ISLA110P50 fn7606 rev 2.00 page 11 of 34 july 25, 2011 figure 11. power vs f sample in 3ma lvds mode figure 12. differential nonlinearity figure 13. integral nonlinearity fi gure 14. snr and sfdr vs vcm figure 15. noise histogram figure 16. single-tone spectrum @ 105mhz typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = 500msps. (continued) 300 350 400 450 500 550 250m 300m 350m 400m 450m 500m sample rate (hz) total power (mw) -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 200 400 600 800 1k code dnl (lsbs) -0.2 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 200 400 600 800 1k code inl (lsbs) 50 55 60 65 70 75 80 85 90 300 350 400 450 500 550 600 650 700 750 800 v cm (mv) snrfs (dbfs) and sfdr (dbc) sfdr snr 01855 9961133 42244 0 0m 2m 4m 6m 8m 10m 12m 512 513 514 515 516 code number of hits -110 -90 -70 -50 -30 -10 0m 50m 100m 150m 200m 250m frequency (hz) amplitude (dbfs) a in = -1.0dbfs snr = 60.69dbfs sfdr = 84.47dbc sinad = 60.67dbfs
ISLA110P50 fn7606 rev 2.00 page 12 of 34 july 25, 2011 figure 17. single-tone spectrum @ 190mhz figure 18. single-tone spectrum @ 495mhz figure 19. single-tone spectrum @ 995mhz figure 20. two-tone spectrum @ 70mhz (1mhz spacing) figure 21. two-tone spectrum @ 170mhz (1mhz spacing) figure 22. input frequency sweep with i2e frozen, i2e previously calibrated @ 105mhz typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = 500msps. (continued) -110 -90 -70 -50 -30 -10 0m 50m 100m 150m 200m 250m frequency (hz) amplitude (dbfs) a in = -1.0dbfs snr = 60.67dbfs sfdr = 82.04dbc sinad = 60.62dbfs -110 -90 -70 -50 -30 -10 0m 50m 100m 150m 200m 250m frequency (hz) amplitude (dbfs) a in = -1.0dbfs snr = 60.34dbfs sfdr = 70.55dbc sinad = 59.97dbfs -110 -90 -70 -50 -30 -10 amplitude (dbfs) 0m 50m 100m 150m 200m 250m frequency (hz) a in = -1.0dbfs snr = 59.13dbfs sfdr = 49.20dbc sinad = 48.43dbfs -120 -100 -80 -60 -40 -20 0 0m 50m 100m 150m 200m 250m frequency (hz) amplitude (dbfs) imd = 88.4dbc -120 -100 -80 -60 -40 -20 0 0m 50m 100m 150m 200m 250m frequency (hz) amplitude (dbfs) imd = 90.4dbc 40 45 50 55 60 65 70 75 80 85 90 0m 50m 100m 150m 200m 250m frequency (hz) snrfs (dbfs) and sfdr (dbc) snr sfdr
ISLA110P50 fn7606 rev 2.00 page 13 of 34 july 25, 2011 figure 23. input frequency sweep with i2e frozen, i2e previously calibrated @ 330mhz figure 24. temperature sweep with i2e frozen, i2e previously calibrated figure 25. analog supply voltage sweep with i2e frozen, i2e previously calibrated typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = 500msps. (continued) 55 60 65 70 75 80 250m 300m 350m 400m 450m 500m frequency (hz) snrfs (dbfs) and sfdr (dbc) snr sfdr 50 55 60 65 70 75 80 85 -40-200 20406080 temperature (c) snrfs (dbfs) and sfdr (dbc) snr sfdr 50 55 60 65 70 75 80 85 90 1.65 1.70 1.75 1.80 1.85 1.90 1.95 supply voltage (avdd) snrfs (dbfs) and sfdr (dbc) snr sfdr
ISLA110P50 fn7606 rev 2.00 page 14 of 34 july 25, 2011 theory of operation functional description the ISLA110P50 is based upon a 12-bit, 250msps a/d converter core that utilizes a pipelined successive approximation architecture (figure 26). the input voltage is captured by a sample-hold amplifier (sha) and converted to a unit of charge. proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. decisions made during the successive appr oximation operations determine the digital code for each inpu t value. the converter pipeline requires twelve samples to produce a result. digital error correction is also applied, resultin g in a total latency of 17 clock cycles. this is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. the device contains two core a/d converters with carefully matched transfer characteristic s. the cores are clocked on alternate clock edges, resulting in a doubling of the sample rate. time?interleaved a/d systems can exhibit non?ideal artifacts in the frequency domain if the individual core a/d characteristics are not well matched. gain, offs et and timing skew mismatches are of primary concern. the intersil interleave engine (i2e) performs automatic interleave calibration for the offset, gain, and sample time skew mismatch between the core a/ds. the i2e circuitry also adjusts in real-time for temperature and voltage variations. residual gain and sample time skew mismatch result in fundamental image spurs at f nyquist f in . offset mismatches create spurs at dc and multiples of f nyquist . power-on calibration as mentioned previously, the cores perform a self-calibration at start-up. an internal power-on-reset (por) circuit detects the supply voltage ramps and initia tes the calibration when the analog and digital supply voltag es are above a threshold. the following conditions must be adhered to for the power-on calibration to execute successfully: ? a frequency-stable conversion clock must be applied to the clkp/clkn pins ? dnc pins must not be connected ?sdo (pin 66) must be high ? resetn (pin 25) must begin low ? spi communications must not be attempted a user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. pins 3, 4, and sdo require an external 4.7k ? pull-up to ovdd. if these pins are pulled low externally during power-up, calibration will not be executed properly. after the power supply has stabilized the internal por releases resetn and an internal pull-up pulls it high, which starts the calibration sequence. if a subseq uent user-initiated reset is desired, the resetn pin should be connected to an open-drain driver with a drive strength in its high impedance state of less than 0.5ma. the calibration sequence is initiated on the rising edge of resetn, as shown in figure 27. th e over-range output (or) is set high once resetn is pulled low, and remains in that state until calibration is complete. the or output returns to normal operation at that time, so it is important that the analog input be within the converter?s full-scale ra nge to observe the transition. if the input is in an over-range condition the or pin will stay high, and it will not be possible to de tect the end of the calibration cycle. digital error correction sha 1.25v inp inn clock generation 2.5-bit flash 6-stage 1.5-bit/stage 3-stage 1-bit/stage 3-bit flash lvds/lvcmos outputs + C figure 26. a/d core block diagram
ISLA110P50 fn7606 rev 2.00 page 15 of 34 july 25, 2011 while resetn is low, the output clock (clkoutp/clkoutn) is set low. normal operation of th e output clock resumes at the next input clock edge (clkp/clkn) after resetn is deasserted. at 500msps the nominal calibrat ion time is 200ms, while the maximum calibration time is 550ms. user initiated reset recalibration of the a/d can be initiated at any time by driving the resetn pin low for a minimum of one clock cycle. an open-drain driver with a drive strength in its high impedance state of less than 0.5ma is re commended, as resetn has an internal high impedance pull-up to ovdd. as is the case during power-on reset, the sdo, resetn and dnc pins must be in the proper state for the calibration to successfully execute. the performance of the ISLA110P50 changes with variations in temperature, supply voltage or sample rate. the extent of these changes may necessitate recalibr ation, depending on system performance requirements. best performance will be achieved by recalibrating the a/d under the environmental conditions at which it will operate. a supply voltage variation of less than 100mv will generally result in an snr change of le ss than 0.5dbfs and sfdr change of less than 3dbc. in situations where the sample ra te is not constant, best results will be obtained if the device is calibrated at the highest sample rate. reducing the sample rate by less than 80msps will typically result in an snr change of less than 0.5dbfs and an sfdr change of less than 3dbc. figures 28 and 29 show the effe ct of temperature on snr and sfdr performance with power-on calibration performed at -40c, +25c, and +85c. each plot shows the variation of snr/sfdr across temperature after a single power-on calibration at -40c, +25c an d +85c. best performance is typically achieved by a user-initi ated power-on calibration at the operating conditions, as stated ea rlier. however, it can be seen that performance drift with temp erature is not a very strong function of the temperature at wh ich the power-on calibration is performed. to achieve the perf ormance demonstrated in the sfdr plot, i2e must be in track mode. analog input a single fully differential input (vinp/vinn) connects to the sample and hold amplifier (sha) of each unit a/d. the ideal full-scale input voltage is 1.45v, centered at the vcm voltage of 0.535v as shown in figure 30. best performance is obtained when the analog inputs are driven differentially. the common-mode output voltage, vcm, should be used to properly bias the inputs as shown in figures 31 through 33. an rf transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (if) inputs. two different transf ormer input schemes are shown in figures 31 and 32. figure 27. calibration timing clkp clkn clkoutp resetn orp calibration begins calibration complete calibration time -4 -3 -2 -1 0 1 2 3 -40 -15 10 35 60 85 snr change (dbfs) cal done at +85c temperature (c) cal done at -40c cal done at +25c -15 -10 -5 0 5 10 15 -40 -15 10 35 60 85 sfdr change (dbc) temperature (c) cal done at -40c cal done at +25c cal done at +85c 1.0 1.8 0.6 0.2 1.4 inp inn vcm 0.535v 0.725v
ISLA110P50 fn7606 rev 2.00 page 16 of 34 july 25, 2011 this dual transformer scheme is used to improve common-mode rejection, which keeps the co mmon-mode level of the input matched to vcm. the value of the shunt resistor should be determined based on the desired load impedance. the differential input resistance of the ISLA110P50 is 500 ? . the sha design uses a switched capacitor input stage (see figure 47), which creates current spikes when the sampling capacitance is reconnected to the input voltage. this causes a disturbance at the input which must settle before the next sampling point. lower source impedance will result in faster settling and improved performance. therefore a 1:1 transformer and low shunt resistance are recommended for optimal performance. a differential amplifier, as shown in figure 33, can be used in applications that require dc-coupl ing. in this configuration, the amplifier will typically dominate the achievable snr and distortion performance. clock input the clock input circuit is a differential pair (see figure 48). driving these inputs with a high level (up to 1.8v p-p on each input) sine or square wave will provide the lowest jitter performance. a transformer with 4:1 impedance ra tio will provide increased drive levels. the clock input is function al with ac-coupled lvds, lvpecl, and cml drive levels. to maintain the lowest possible aperture jitter, it is recommended to have high slew rate at the zero crossing of the differential clock input signal. the recommended drive circuit is shown in figure 34. a duty range of 40% to 60% is acceptable. the clock can be driven single-ended, but this will reduce the edge rate and may impact snr performance. the clock inputs are internally self-biased to avdd/2 to facilitate ac coupling. jitter in a sampled data system, cloc k jitter directly impacts the achievable snr performance. the theoretical relationship between clock jitter (t j ) and snr is shown in equation 1 and is illustrated in figure 35. this relationship shows the snr that would be achieved if clock jitter were the only non-ideal factor. in reality, achievable snr is limited by internal factors such as linearity, aperture jitter and thermal noise. internal aperture jitter is the uncertainty in the sampling instant shown in figure 3. the internal aperture jitter combines with the input clock jitt er in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. the total jitter, combined with other noise sources, then determines the achievable snr. figure 31. transformer input for general purpose applications adt1-1wt 0.1f a/d vcm adt1-1wt 1000pf figure 32. transmission line transformer input for high if applications adtl1-12 0.1f a/d vcm adtl1-12 1000pf 1000pf figure 33. differential amplifier input a/d vcm 0.1f 0.22f 69.8o 49.9o 100o 100o 69.8o 348o 348o cm 217o 25o 25o ? ? ? ? ? ? ? ? ? ? figure 34. recommended clock drive tc4-1w 200pf avdd 200o 200pf 200pf clkp clkn 1ko 1ko 1000pf ? ? ? ? f in t j ------------------- ?? ?? = (eq. 1) figure 35. snr vs clock jitter tj = 100ps tj = 10ps tj = 1ps tj = 0.1ps 10 bits 12 bits 14 bits 50 55 60 65 70 75 80 85 90 95 100 1m 10m 100m 1g snr (db) input frequency (hz)
ISLA110P50 fn7606 rev 2.00 page 17 of 34 july 25, 2011 voltage reference a temperature compensated voltage reference provides the reference charges used in the su ccessive approximat ion operations. the full-scale range of each a/d is proportional to the reference voltage. the nominal value of the voltage reference is 1.25v. digital outputs output data is available as a pa rallel bus in lvds-compatible or cmos modes. in either case, the da ta is presented in double data rate (ddr) format. figures 3 and 4 show the timing relationships for lvds and cmos modes, respectively. additionally, the drive current for lvds mode can be set to a nominal 3ma or a power-saving 2ma. the lower current setting can be used in designs where the receiver is in close physical proximity to the a/d. the applicability of this setting is dependent upon the pcb layout, therefore the user should experiment to determine if performance degradation is observed. the output mode and lvds drive current are selected via the outmode pin as shown in table 1. the output mode can also be controlled through the spi port, which overrides the outmode pin setting. details on this are contained in ?serial peripheral interface? on page 22. an external resistor creates the bias for the lvds drivers. a 10k ? , 1% resistor must be connected from the rlvds pin to ovss. over-range indicator the over-range (or) bit is asserted when the output code reaches positive full-scale (e.g., 0xfff in offset binary mode). the output code does not wrap around during an over-range condition. the or bit is updated at the sample rate. power dissipation the power dissipated by the ISLA110P50 is primarily dependent on the sample rate and the output modes: lvds vs cmos and ddr vs sdr. there is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. the output supply dissipation changes to a lesser degree in lvds mode, but is more strongly related to the clock frequency in cmos mode. nap/sleep portions of the device may be shut down to save power during times when operation of the a/d is not required. two power saving modes are available: nap and sleep. nap mode reduces power dissipation to less than 164mw and recovers to normal operation in approximately 2.75s. sleep mode reduces power dissipation to less than 6mw but requires approximately 1ms to recover from a sleep command. wake-up time from sleep mode is dependent on the state of csb; in a typical application csb would be held high during sleep, requiring a user to wait 150s max after csb is asserted (brought low) prior to writing ?001x? to spi register 25. the device would be fully powered up, in normal mode 1ms after this command is written. wake-up from sleep mode sequence (csb high) ?pull csb low ? wait 150s ? write ?001x? to register 25 ? wait 1ms until a/d fully powered on in an application where csb was kept low in sleep mode, the 150s csb setup time is not required as the spi registers are powered on when csb is low, the chip power dissipation increases by ~15mw in this case. the 1ms wake-up time after the write of a ?001x? to register 25 still applies. it is generally recommended to keep csb high in sleep mode to avoid any unintentional spi activity on the a/d. all digital outputs (data, clkout and or) are placed in a high impedance state during nap or sleep. the input clock should remain running and at a fixed fr equency during nap or sleep, and csb should be high. recovery time from nap mode will increase if the clock is stopped, since the internal dll can take up to 52s to regain lock at 250msps. by default after the device is powered on, the operational state is controlled by the napslp pin as shown in table 2. the power-down mode can also be controlled through the spi port, which overrides the napslp pin setting. details on this are contained in ?serial peripheral in terface? on page 22. this is an indexed function when controlled from the spi, but a global function when driven from the pin. data format output data can be presented in three formats: two?s complement, gray code and offset binary. the data format is selected via the outfmt pin as shown in table 3. the data format can also be controlled through the spi port, which overrides the outfmt pin setting. details on this are contained in ?serial peripher al interface? on page 22. table 1. outmode pin settings outmode pin mode avss lvcmos float lvds, 3ma avdd lvds, 2ma table 2. napslp pin settings napslp pin mode avss normal float sleep avdd nap table 3. outfmt pin settings outfmt pin mode avss offset binary float two?s complement avdd gray code
ISLA110P50 fn7606 rev 2.00 page 18 of 34 july 25, 2011 offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the mo st positive input to 0xfff (all ones). two?s complement coding simply complements the msb of the offset binary representation. when calculating gray code the msb is unchanged. the remaining bits are computed as the xor of the current bit position and the next most significant bit. figure 36 shows this operation. converting back to offset binary from gray code must be done recursively, using the result of each bit for the next lower bit as shown in figure 37. mapping of the input voltage to the various data formats is shown in table 4. i2e requirements and restrictions overview i2e is a blind and background capable algorithm, designed to transparently eliminate interleavi ng artifacts. this circuitry eliminates interleave artifacts due to offset, gain, and sample time mismatches between unit a/ds, and across supply voltage and temperature variations in real-time. differences in the offset, gain, and sample times of time-interleaved a/ds create artifacts in the digital outputs. each of these artifacts creates a unique signature that may be detectable in the captured samples. the i2e algorithm optimizes performance by detecting error signatures and adjusting each unit a/d using minimal additional power. the i2e algorithm can be put in active run state via spi. when the i2e algorithm is in active run state, it detects and corrects for offset, gain, and sample time mismatches in real time (see track mode description in the ?active run state? section). however, certain analog input characteristics can obscure the estimation of these mismatches. the i2e algorithm is capable of detecting these obscuring analog input characteristics, and as long as they are present, i2e wi ll stop updating the correction in real time. effectively, this freezes the current correction circuitry to the last known good state (see hold mode description in the ?active run state? section). once the analog input signal stops obscuring the interleaved artifacts, the i2e algorithm will automatically start correcting fo r mismatch in real time again. active run state during the active run state the i2e algorithm acti vely suppresses artifacts due to interleaving base d on statistics in the digitized data. i2e has two modes of operation in this state (described below), dynamically chosen in real-time by the algorithm based on the statistics of the analog input signal. track mode refers to the default state of the algorithm, when all artifacts due to interleaving are actively being eliminated. to be in track mode the analog input si gnal to the device must adhere to the following requirements: ? possess total power greater than -20dbfs, integrated from 1mhz to nyquist but excluding signal energy in a 100khz band centered at f s /4 figure 36. binary to gray code conversion 10 11 9 0 1 binary 10 11 9 0 gray code ? ? ? ? ? ? ? ? ? ? ? ? 1 figure 37. gray code to binary conversion 10 11 9 0 1 binary 10 11 9 0 gray code ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? ?
ISLA110P50 fn7606 rev 2.00 page 19 of 34 july 25, 2011 the criteria above assumes 500msps operation; the frequency bands should be scaled proporti onally for lower sample rates. note that the effect of exclud ing energy in the 100khz band around of f s /4 exists in every nyquist zone. this band generalizes to the form (n*f s /4-50khz) to (n*f s /4+50khz), where n is any odd integer. an input signal that violates these criteria briefly (approximately 10s), before and after which it meets this criteria, will not impact system performance. the algorithm must be in track mode for approximately one second (defined as i2epost_t in the specification table on page 7) after power-up before the specifications apply. once this requirement has been met, the specifications of the device will continue to be met while i2e rema ins in track mode, even in the presence of temperature and supply voltage changes. hold mode refers to the state of the i2e algorithm when the analog input signal does not meet the requirements specified above. if the algorithm detects th at the signal no longer meets the criteria, it automatically enters hold mode. in hold mode, the i2e circuitry freezes the adjustme nt values based on the most recent set of valid input conditio ns. however, in hold mode, the i2e circuitry will not correct for new changes in interleave artifacts induced by supply vo ltage and temperature changes. the i2e circuitry will remain in hold mode until such time as the analog input signal meets the requirements for track mode. power meter the power meter calculates the average power of the analog input, and determines if it?s within range to allow operation in track mode. both ac rms and total rms power are calculated, and there are separate spi programmable thresholds and hysteresis values for each. notch filter a digital filter removes the signal energy in a 100khz band around f s /4 before the i2e circuitr y uses these samples for estimating offset, gain, and sa mple time mismatches (data samples produced by the a/d are unaffected by this filtering). this allows the i2e algorithm to continue in active run state while in the presence of a large amount of input energy near the f s /4 frequency. this filter can be powered down if it?s known that the signal characteristics won?t vi olate the restrictions. powering down the notch filter will reduce power consumption by approximately 70mw. nyquist zones the i2e circuitry allows the use of any one nyquist zone without configuration, but requires the use of only one nyquist zone. inputs that switch dynamica lly between nyquist zones will cause poor performance for the i2e circuitry. for example, i2e will function properly for a particular application that has f s = 500msps and uses the 1 st nyquist zone (0mhz to 250mhz). i2e will also function properly for an application that uses f s = 500msps and the 2 nd nyquist zone (250mhz to 500mhz). i2e will not function properly for an application that uses f s = 500msps, and input frequency bands from 150mhz to 210mhz and 250mhz to 290mhz simultaneously. there is no need to configure the i2e algori thm to use a particular nyquist zone, but no dynamic switching between nyquist zones is permitted while i2e is running. configurability and communication i2e can respond to status queries, be turned on and turned off, and generally configured via spi programmable registers. configuring of i2e is generally unnecessary unless the application cannot meet the requ irements of track mode on or after power up. parameters that can be adjusted and read back include notch filter threshold an d status, power meter threshold and status, and initial values for the offset, gain, and sample time values to use when i2e starts.
ISLA110P50 fn7606 rev 2.00 page 20 of 34 july 25, 2011 clock divider synchronous reset an output clock (clkoutp, clkout n) is provided to facilitate latching of the sampled data. this clock is at half the frequency of the sample clock, and the absolute phase of the output clocks for multiple a/ds is indeterminat e. this feature allows the phase of multiple a/ds to be synchronized (refer to figure 38), which greatly simplifies data capture in systems employing multiple a/ds. the reset signal must be well-ti med with respect to the sample clock (see ?switching specifications? on page 9). figure 38. synchronous reset operation s1 s2 s0 s3 s1 s2 s0 s3 clkdivrstp 2 adc1 output data adc1 clkoutp adc2 clkoutp (phase 1) 3 adc2 clkoutp (phase 2) 3 3 either output clock phase (phase 1 or phase 2 ) equally likel y prior to synchronization s1 l+t d 1 1 delay equals fixed pipeline latency (l cycles) plus fixed ana log propagation delay t d t rsth t rsts t rstrt adc2 output data analog input sample clock input clkdivrstn is not shown, but must be driven, and is the complim ent of clkdivrstp s2 2 clkdivrstp setup and hold times are with respec t to i nput sample clock rising edge.
ISLA110P50 fn7606 rev 2.00 page 21 of 34 july 25, 2011 figure 39. msb-first addressing csb sclk sdio r/w w1 w0 a12 a11 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a10 figure 40. lsb-first addressing csb sclk sdio r/w w1 w0 a12 a11 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a2 figure 41. spi write t s t hi t clk t lo r/w w1w0a12a11a10a9a8a7 d5 d4 d3 d2 d1 d0 t h t dhw t dsw spi write csb sclk sdio figure 42. spi read (3 wire mode) (4 wire mode) r/w w1 w0 a12 a11 a10 a9 a2 a1 d7 d6 d3 d2 d1 d7 d3 d2 d1 d0 a0 writing a read co mmand reading data d0 t h t dhr t dvr spi read t hi t clk t lo t dhw t dsw t s csb sclk sdio sdo
ISLA110P50 fn7606 rev 2.00 page 22 of 34 july 25, 2011 serial peripheral interface a serial peripheral interface (spi) bus is used to facilitate configuration of the device and to optimize performance. the spi bus consists of chip select (csb), serial clock (sclk) serial data output (sdo), and serial data input/output (sdio). the maximum sclk rate is equal to the a/d sample rate (f sample ) divided by 32 for write operations and f sample divided by 132 for reads. at f sample = 250mhz, maximum sclk is 15.63mhz for writing and 3.79mhz for read operations. there is no minimum sclk rate. the following sections describe various registers that are used to configure the spi or adjust perfor mance or functional parameters. many registers in the available address space (0x00 to 0xff) are not defined in this document. additionally, within a defined register there may be certain bits or bit combinations that are reserved. undefined registers and undefined values within defined registers are reserved and should not be selected. setting any reserved register or value may produce indeterminate results. spi physical interface the serial clock pin (sclk) provid es synchronization for the data transfer. by default, all data is presented on the serial data input/output (sdio) pin in three-wire mode. the state of the sdio pin is set automatically in the communication protocol (described in the following). a dedicated serial data output pin (sdo) can be activated by setting 0x00[7] high to allow operation in four-wire mode. the spi port operates in a half duplex master/slave configuration, with the isla11 0p50 functioning as a slave. multiple slave devices can inte rface to a single master in three-wire mode only, since the sdo output of an unaddressed device is asserted in four wire mode. the chip-select bar (csb) pin determines when a slave device is being addressed. multiple slav e devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in three- wire mode). if multiple slave devices are selected for reading at the same time, the results will be indeterminate. the communication protocol begins with an instruction/address phase. the first rising sclk edge following a high to low transition on csb determines the beginning of the two-byte instruction/address command; sclk must be static low before the csb transition. data can be presented in msb-first order or lsb-first order. the default is msb-first, but this can be changed by setting 0x00[6] high. figure s 39 and 40 show the appropriate bit ordering for the msb-first and lsb-first modes, respectively. in msb-first mode, the address is incremented for multi-byte transfers, while in lsb-fi rst mode it?s decremented. in the default mode, the msb is r/ w, which determines if the data is to be read (active high) or writ ten. the next two bits, w1 and w0, determine the number of data bytes to be read or written (see table 5). the lower 13 bits contai n the first address for the data transfer. this relationship is illu strated in figure 41, and timing values are given in ?switchi ng specifications? on page 9. after the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the a/d (based on the r/w bit status). the data transfer will continue as long as csb remains low and sclk is active. stalling of the csb pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. for transfers of four bytes or more, csb is allowed to stall in the middle of the instruction/address bytes or before the first data byte. if csb transitions to a high state after that point the state machine will reset and terminate the data transfer. figures 43 and 44 illustrate the ti ming relationships for 2-byte and n-byte transfers, respectively. the operation for a 3-byte transfer can be inferred from these diagrams. figure 43. 2-byte transfer csb sclk sdio instruction/address data word 1 data word 2 csb stalling figure 44. n-byte transfer csb sclk sdio instruction/address data word 1 data word n last legal csb stalling
ISLA110P50 fn7606 rev 2.00 page 23 of 34 july 25, 2011 spi configuration address 0x00: chip_port_config bit ordering and spi reset are contro lled by this register. bit order can be selected as msb to lsb (m sb first) or lsb to msb (lsb first) to accommodate various micro controllers. bit 7 sdo active bit 6 lsb first setting this bit high configures the spi to interpret serial data as arriving in lsb to msb order. bit 5 soft reset setting this bit high resets all spi registers to default values. bit 4 reserved this bit should always be set high. bits 3:0 these bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. address 0x02: burst_end if a series of sequential register s are to be set, burst mode can improve throughput by eliminating redundant addressing. in 3-wire spi mode the burst is ended by pulling the csb pin high. if the device is operated in 2-wire mode the csb pin is not available. in that case, setting the burst_end address determines the end of the transfer. during a write operation, the user must be cautious to transmit the corre ct number of bytes based on the starting and ending addresses. bits 7:0 burst end address this register value determines the ending address of the burst data. device information address 0x08: chip_id address 0x09: chip_version the generic die identifier and a revision number, respectively, can be read from these two registers. indexed device configuration/control address 0x10: device_index_a bits 1:0 adc01, adc00 determines which a/d is addressed. valid states for this register are 0x01 or 0x10. the two a/d cores cannot be adjusted concurrently. a common spi map, which can ac commodate single-channel or multi-channel devices, is used for all intersil a/d products. certain configuration commands (i dentified as indexed in the spi map) can be executed on a per-converter basis. this register determines which converter is being addressed for an indexed command. it is important to note that only a single converter can be addressed at a time. this register defaults to 00h, indicating that no a/d is addressed. error code ?ad? is returned if any indexed register is read from without properly setting device_index_a. address 0x20: offset_coarse address 0x21: offset_fine the input offset of the a/d core can be adjusted in fine and coarse steps. both adjustments are made via an 8-bit word as detailed in table 6. the data format is two?s complement. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. address 0x22: gain_coarse address 0x23: gain_medium address 0x24: gain_fine gain of the a/d core can be adjusted in coarse, medium and fine steps. coarse gain is a 4-bit adjustment while medium and fine are 8-bit. multiple coarse gain bits can be set for a total adjustment range of 4.2%. (?0011? ? -4.2% and ?1100? ? +4.2%) it is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 23h and 24h. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. table 6. offset adjustments parameter 0x20[7:0] coarse offset 0x21[7:0] fine offset steps 255 255 ?full scale (0x00) -133lsb (-47mv) -5lsb (-1.75mv) mid?scale (0x80) 0.0lsb (0.0mv) 0.0lsb +full scale (0xff) +133lsb (+47mv) +5lsb (+1.75mv) nominal step size 1.04lsb (0.37mv) 0.04lsb (0.014mv) table 7. coarse gain adjustment 0x22[3:0] nominal coarse gain adjust (%) bit3 +2.8 bit2 +1.4 bit1 -2.8 bit0 -1.4
ISLA110P50 fn7606 rev 2.00 page 24 of 34 july 25, 2011 address 0x25: modes two distinct reduced power modes can be selected. by default, the tri-level napslp pin can sele ct normal operation, nap or sleep modes (refer to?nap/sleep? on page 17). this functionality can be overridden and controlled through the spi. this is an indexed function when controlled from the spi, but a global function when driven from the pin. this register is not changed by a soft reset. address 0x30: i2e status the i2e general status register. bits 0 and 1 indicate if the i2e circuitry is in active run or hold state. the state of the i2e circuitry is dependent on the analog input signal itself. if the input signal obscures the interleave mismatched artifacts such that i2e cannot estimate the mismatch, the algorithm will dynamically enter the hold state. for example, a dc mid-scale input to the a/d does not contain sufficient information to estimate the gain and sample time skew mismatches, and thus the i2 e algorithm will enter the hold state. in the hold state, the an alog adjustments for interleave correction will be frozen and mismatch estimate calculations will cease until such time as the an alog input achieves sufficient quality to allow the i2e algorithm to make mismatch estimates again. bit 0: 0 = i2e has not detected a low power condition. 1 = i2e has detected a low power condition, and the analog adjustments for interleave correction are frozen. bit 1: 0 = i2e has not detected a low ac power condition. 1 = i2e has detected a low ac power condition, and i2e will continue to correct with best known inform ation but will not update its interleave correction adjustments until the input signal achieves sufficient ac rms power. bit 2: when first started, the i2e algorithm can take a significant amount of time to settle (~1s), dependent on the characteristics of the analog input signal. 0 = i2e is still settling, 1 = i2e has completed settling. address 0x31: i2e control the i2e general control register. th is register can be written while i2e is running to control various parameters. bit 0: 0 = turn i2e off, 1= turn i2e on bit 1: 0 = no action, 1 = freeze i2e, leaving all settings in the current state. subsequently writing a 0 to this bit will allow i2e to continue from the state it was left in. bit 2-4: disable any of the interleave adjustments of offset, gain, or sample time skew bit 5: 0 = bypass notch filter, 1 = use notch filter on incoming data before estimating interleave mismatch terms address 0x32: i2e static control the i2e general static control re gister. this register must be written prior to turning i2e on for the settings to take effect. bit 1-4: reserved, always set to 0 bit 5: 0 = normal operation, 1 = skip coarse adjust ment of the offset, gain, and sample time skew analog controls when i2e is first turned on. this bit would typi cally be used if optimal analog adjustment values for offset, gain, and sample time skew have been preloaded in order to have the i2e algorithm converge more quickly. the system gain of the pair of interleaved core a/ds can be set by programming the medium and fine gain of the reference a/d before turning i2e on. in this case, i2e will adjust the non-reference a/d?s gain to ma tch the reference a/d?s gain. bit 7: reserved, always set to 0 address 0x4a: i2e power down this register provides the capability to completely power down the i2e algorithm and the notch fi lter. this would typically be done to conserve power. bit 0: power down the i2e algorithm bit 1: power down the notch filter address 0x50-0x55: i2e freeze thresholds this group of registers provides programming access to configure i2e?s dynamic freeze control. as with any interleave mismatch correction algorithm making estimates of the interleave mismatch errors using the digitized application input signal, there are certain characteristics of the input signal that can obscure the mismatch estimates. for example, a dc input to the a/d contains no information about the sample time skew mismatch between the core a/ds, and thus should not be used by the i2e algorithm to update its sample time skew estimate. under such circumstances, i2e en ters hold state. in the hold state, the analog adjustments will be frozen and mismatch estimate calculations will cease until such time as the analog input achieves sufficient quality to allow the i2e algorithm to make mismatch estimates again. these registers allow the programming of the thresholds of the meters used to determine the quality of the input signal. this can be used by the application to optimize i2e?s behavior based on knowledge of the input signal. for example, if a specific table 8. medium and fine gain adjustments parameter 0x23[7:0] medium gain 0x24[7:0] fine gain steps 256 256 ?full scale (0x00) -2% -0.20% mid?scale (0x80) 0.00% 0.00% +full scale (0xff) +2% +0.2% nominal step size 0.016% 0.0016% table 9. power-down control value 0x25[2:0] power down mode 000 pin control 001 normal operation 010 nap mode 100 sleep mode
ISLA110P50 fn7606 rev 2.00 page 25 of 34 july 25, 2011 application had an input signal that was typically 30db down from full scale, and was prim arily concerned about analog performance of the a/d at this input power, lowering the rms power threshold would allow i2e to continue tracking with this input power level, thus allowing it to track over voltage and temperature changes. 0x50 (lsbs), 0x51 (msbs) rms power threshold this 16-bit quantity is the rms power threshold at which i2e will enter hold state. the rms power of the analog input is calculated continuously by i2e on incoming data. a 12-bit number squared produc es a 24-bit result (for a/d resolutions under 12-bits, the a/d samples are msb-aligned to 12-bit data). a dynamic number of these 24-bit results are averaged to compare with this threshold approximately every 1s to decide whether or not to freeze i2e. the 24-bit threshold is constructed with bits 23 through 20 (msbs) assigned to 0, bits 19 through 4 assigned to this 16-bit quantity, and bits 3 through 0 (lsbs) assigned to 0. as an ex ample, if the application wanted to set this threshold to trigger near the rms analog input of a -20dbfs sinusoidal input, the calculation to determine this register?s value would be therefore, programming 0x1488 into these two registers will cause i2e to freeze when the si gnal being digitized has less rms power than a -20dbfs sinusoid. the default value of this register is 0x1000, causing i2e to freeze when the input amplitude is less than -21.2 dbfs. the freezing of i2e by the rms power meter threshold affects the gain and sample time skew interleave mismatch estimates, but not the offset mismatch estimate. 0x52 rms power hysteresis in order to prevent i2e from constantly oscillating between the hold and track state, there is hysteresis in the comparison described above. after i2e enters a frozen state, the rms input power must achieve ? ? threshold value + hysteresis to again enter the track state. the hysteresis quantity is a 24-bit value, constructed with bits 23 through 12 (msbs) being assigned to 0, bits 11 through 4 assigned to this register?s value, and bits 3 through 0 (lsbs) assigned to 0. ac rms power threshold similar to rms power threshold, there must be sufficient ac rms power (or dv/dt) of the input signal to measure sample time skew mismatch for an arbitrary input. this is clear from observing the effect when a high voltage (and therefore large rms value) dc input is applied to the a/d input. without sufficient dv/dt in the input si gnal, no information about the sample time skew between the core a/ds can be determined from the digitized samples. the ac rms power meter is implemented as a high-passed (via dsp) rms power meter. the writing of the ac rms power threshold is different than other spi registers, and these regi sters are not listed in the spi memory map table. the required algorithm is documented below. 1. write the value 0x80 to the index register (spi address 0x10) 2. write the msbs of the 16-bit quantity to spi address 0x150 3. write the lsbs of the 16-bit quantity to spi address 0x14f a 12-bit number squared produces a 24-bit result (for a/d resolutions under 12-bits, the a/d samples are msb-aligned to 12-bit data). a dynamic number of these 24-bit results are averaged to compare with this threshold approximately every 1s to decide whether or not to freeze i2e. the 24-bit threshold is constructed with bits 23 through 20 (msbs) assigned to 0, bits 19 through 4 assigned to this 16-bit quantity, and bits 3 through 0 (lsbs) assigned to 0. the calc ulation methodology to set this register is identical to the desc ription in the rms power threshold description. the freezing of i2e when the ac rms power meter threshold is not met affects the sample time skew interleave mismatch estimate, but not the offset or gain mismatch estimates. 0x55 ac rms power hysteresis in order to prevent i2e from constantly oscillating between the hold and track state, there is hysteresis in the comparison described above. after i2e enters a frozen state, the ac rms input power must achieve ? threshold value + hysteresis to again enter the track state. the hysteresis quantity is a 24-bit value, constructed with bits 23 through 12 (msbs) being assigned to 0, bits 11 through 4 assigned to this register?s value, and bits 3 through 0 (lsbs) assigned to 0. address 0x60-0x64: i2e initialization these registers provide access to the initialization values for each of offset, gain, and sample time skew that i2e programs into the target core a/d before adjusting to minimize interleave mismatch. they can be used by the system to, for example, reduce the convergence time of the i2e algorithm by programming in the optimal values before turning i2e on. in this case, i2e only needs to adjust for temperature and vo ltage-induced changes since the optimal values were recorded. global device conf iguration/control address 0x70: skew_diff the value in the skew_diff register adjusts the timing skew between the two a/d cores. the nominal range and resolution of this adjustment are given in table 10. the default value of this register after power-up is 80h. rms codes 2 2 ------- 10 20 C 20 --------- - ?? ?? ? 2 12 290codes ? ? = (eq. 2) hex 290 2 ?? 0x014884 truncatemsbandlsbhexdigit 0x1488 = = (eq. 3) table 10. differential skew adjustment parameter 0x70[7:0] differential skew steps 256 ?full scale (0x00) -6.5ps mid?scale (0x80) 0.0ps +full scale (0xff) +6.5ps nominal step size 51fs
ISLA110P50 fn7606 rev 2.00 page 26 of 34 july 25, 2011 address 0x71: phase_slip the output data clock is generated by dividing down the a/d input sample clock. some system s with multiple a/ds can more easily latch the data from each a/d by controlling the phase of the output data clock. this control is accomplished through the use of the phase_slip spi feature, which allows the rising edge of the output data clock to be adva nced by one input clock period, as shown in the figure 45. execution of a phase_slip command is accomplished by first writing a '0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address 0x71. address 0x73: output_mode_a the output_mode_a register controls the physical output format of the data, as well as the logi cal coding. the ISLA110P50 can present output data in two physical formats: lvds or lvcmos. additionally, the drive strength in lvds mode can be set high (3ma) or low (2ma). by default, the tri-level outmode pin selects the mode and drive level (refer to ?digital outputs? on page 17). this functionality can be overri dden and controlled through the spi, as shown in table 11. data can be coded in three possible formats: two?s complement, gray code or offset binary. by default, the tri-level outfmt pin selects the data format (refer to ?data format? on page 17). this functionality can be overridden and controlled through the spi, as shown in table 12. this register is not changed by a soft reset. address 0x74: output_mode_b address 0x75: config_status bit 6 dll range this bit sets the dll operating range to fast (default) or slow. internal clock signals are generate d by a delay-locked loop (dll), which has a finite operating range. table 13 shows the allowable sample rate ranges for the slow and fast settings. the output_mode_b and config_status registers are used in conjunction to enable ddr mode and select the frequency range of the dll clock generator. the method of setting these options is different from the other registers. the procedure for setting output _mode_b is shown in figure 46. read the contents of output_mode_b and config_status and xor them. then xor this result with the desired value for output_mode_b and write that xor result to the register. device test the ISLA110P50 can produce preset or user defined patterns on the digital outputs to facilitate in -situ testing. a static word can be placed on the output bus, or two different words can alternate. in the alternate mode, the values defined as word 1 and word 2 (as shown in table 14) are set on the output bus on alternating clock phases. the test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. table 11. output mode control value 0x93[7:5] output mode 000 pin control 001 lvds 2ma 010 lvds 3ma 100 lvcmos figure 45. phase slip adc input clock (500mhz) output data clock (250mhz) no clock_slip output data clock (250mhz) 1 clock_slip output data clock (250mhz) 2 clock_slip 2ns 4ns 2ns figure 46. setting output_mode_b register read config_status 0x75 read output_mode_b 0x74 desired value write to 0x74
ISLA110P50 fn7606 rev 2.00 page 27 of 34 july 25, 2011 address 0xc0: test_io bits 7:6 user test mode these bits set the test mode to static (0x00) or alternate (0x01) mode. other values are reserved. the four lsbs in this register (output test mode) determine the test pattern in combination with registers 0xc2 through 0xc5. refer to ?spi memory map? on page 28. address 0xc2: user_patt1_lsb address 0xc3: user_patt1_msb these registers define the lower and upper eight bits, respectively, of the first user-defined test word. address 0xc4: user_patt2_lsb address 0xc5: user_patt2_msb these registers define the lower and upper eight bits, respectively, of the second user-defined test word. digital temperature sensor this set of registers provides digital access to an iptat-based temperature sensor, allowing the system to estimate the temperature of the die. this inform ation is of particular interest for applications that do not keep i2e in active run state when in normal use, allowing easy acce ss to information that can be used to decide when to recalibrate the a/d as needed. this set of registers is not included in the spi memory map table. the most accurate usage of this information requires knowledge of the temperature at which the digital value is first read (time = 0, t(0) = c at time = 0, and register_value(0) = the digital value of the temperature registers at time = 0). any future reading of the registers indicate s temperature change according to equation 4: a less accurate method for eval uating the temperature change does not require knowledge of the temperature at time = 0, and is given by equation 5: the digital temperature sensor is a weak function of the avdd supply voltage, so to achieve best accuracy the avdd supply voltage should be held fairly constant across the operating temperature range. the algorithm to access this set of registers is as follows: 1. write the value 0x80 to the index register (spi address 0x10) 2. write the value 0x88 to spi address 0x120 to turn the temperature sensor on. 3. read the register_value lsbs at spi register 0x11e 4. read the register_value msbs at spi register 0x11f 5. write the value 0x60 to spi address 0x120 to turn the temperature sensor off. table 14. output test modes value 0xc0[3:0] output test mode word 1 word 2 0000 off 0001 midscale 0x8000 n/a 0010 positive full-scale 0xffff n/a 0011 negative full-scale 0x0000 n/a 0100 checkerboard 0xaaaa 0x5555 0101 reserved n/a n/a 0110 reserved n/a n/a 0111 one/zero 0xffff 0x0000 1000 user pattern user_patt1 user_patt2 ? tt1 ?? t0 ?? register_value(1) ?? register_value(0) ?? C t0 ?? 216 C ?? 256 ? ?? --------------------------------------------------------------- ---------------------------------------------- = C = (eq. 4) ? tt1 ?? t0 ?? register_value(1) ?? register_value(0) ?? C -0.72 ?? --------------------------------------------------------------- ---------------------------------------------- = C = (eq. 5)
ISLA110P50 fn7606 rev 2.00 page 28 of 34 july 25, 2011 spi memory map table 15. spi memory map addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex) indexed/gl obal spi config 00 port_config sdo active lsb first soft reset mirror (bit5) mirror (bit6) mirror (bit7) 00h g 01 reserved reserved 02 burst_end burst end address [7:0] 00h g 03-07 reserved reserved info 08 chip_id chip id # read only g 09 chip_version chip version # read only g indexed device config/control 10 device_index_a reserved adc01 adc00 00h i 11-1f reserved reserved 20 offset_coarse coarse offset cal. value i 21 offset_fine fine offset cal. value i 22 gain_coarse reserved coarse gain cal. value i 23 gain_medium medium gain cal. value i 24 gain_fine fine gain cal. value i 25 modes reserved power-down mode [2:0] 000 = pin control 001 = normal operation 010 = nap 100 = sleep other codes = reserved 00h not affected by soft reset i 26-2f reserved reserved i i2e control and status 30 i2e status reserved i2e settled low ac rms power low rms power read only g 31 i2e control enable notch filter disable offset disable gain disable skew freeze run 20h g 32 i2e static control reserved must be set to 0 skip coarse adjustment reserved, must be set to 0 00h g 33-49 reserved reserved g 4a i2e power down notch filter power down i2e power down 00h g 4b-4f reserved reserved g 50 i2e rms power threshold lsbs rms power threshold, lsbs 00h g 51 i2e rms power threshold msbs rms power threshold, msbs 10h g 52 i2e rms hysteresis rms power hysteresis ffh g 53-54 reserved reserved g
ISLA110P50 fn7606 rev 2.00 page 29 of 34 july 25, 2011 i2e control and status (continued) 55 i2e ac rms hysteresis ac rms power hysteresis 10h g 56-5f reserved reserved g 60 coarse offset init coarse offset initialization value 80h g 61 fine offset init fine offset initialization value 80h g 62 medium gain init medium gain initialization value 80h g 63 fine gain init fine gain initialization value 80h g 64 sample time skew init sample time skew initialization value 80h g 65-6f reserved reserved g global deviceconfig/control 70 skew_diff differential skew 80h g 71 phase_slip reserved next clock edge 00h g 72 reserved reserved reserved (must be 0) 00h not affected by soft reset g 73 output_mode_a output mode [2:0] 000 = pin control 001 = lvds 2ma 010 = lvds 3ma 100 = lvcmos other codes = reserved output format [2:0] 000 = pin control 001 = twos complement 010 = gray code 100 = offset binary other codes = reserved 00h not affected by soft reset g 74 output_mode_b dll range 0 = fast 1 = slow 00h not affected by soft reset g 75 config_status xor result read only g 76-bf reserved reserved device test c0 test_io user test mode [1:0] 00 = single 01 = alternate 10 = reserved 11 = reserved output test mode [3:0] 00h g 0 = off 1 = midscale short 2 = +fs short 3 = -fs short 4 = checker board 5 = reserved 6 = reserved 7 = one/zero word toggle 8 = user input 9-15 = reserved c1 reserved reserved 00h g c2 user_patt 1_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h g c3 user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 00h g c4 user_patt 2_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h g c5 user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 00h g c6-ff reserved reserved table 15. spi memory map (continued) addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex) indexed/gl obal
ISLA110P50 fn7606 rev 2.00 page 30 of 34 july 25, 2011 equivalent circuits figure 47. analog inputs figure 48. clock inputs figure 49. tri-level digital in puts figure 50. digital inputs figure 51. lvds outputs figure 52. cmos outputs avdd inp inn avdd f1 f1 f2 f3 f2 f3 csamp 1.6pf csamp 1.6pf to charge pipeline to charge pipeline 500o ? ? ? ? ? ? ? avdd clkp clkn avdd avdd to clock- phase generation 11ko 11ko avdd 18ko 18ko ? ? ? ? avdd input avdd avdd avdd to sense logic 75ko 75ko 75ko 75ko 280o ? ? ? ? ? input ovdd ovdd 280 ? to logic 20k ? ovdd (20k pull-up on resetn only) d[7:0]p ovdd ovdd 2ma or 3ma 2ma or 3ma data data data data d[7:0]n ovdd d[7:0] ovdd ovdd data
ISLA110P50 fn7606 rev 2.00 page 31 of 34 july 25, 2011 a/d evaluation platform intersil offers an a/d evaluation platform which can be used to evaluate any of intersil?s high speed a/d products. the platform consists of an fpga based da ta capture motherboard and a family of a/d daughter cards. th is usb based platform allows a user to quickly evaluate the a/d?s performance at a user?s specific application frequency requirements. more information is available at http://www.intersil.com/converters/adc_eval_platform/ layout considerations split ground and power planes data converters operating at high sampling frequencies require extra care in pc board layout. many complex board designs benefit from isolating the analog and digital sections. analog supply and ground planes should be laid out under signal and clock inputs. locate the digital planes under outputs and logic pins. grounds should be joined under the chip. clock input considerations use matched transmission lines to the transformer inputs for the analog input and clock signals. loca te transformers and terminations as close to the chip as possible. exposed paddle the exposed paddle must be electrically connected to analog ground (avss) and should be connected to a large copper plane using numerous vias for op timal thermal performance. bypass and filtering bulk capacitors should have lo w equivalent series resistance. tantalum is a good choice. for best performance, keep ceramic bypass capacitors very close to device pins. longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. make sure that connections to ground are direct and low impedance. avoid forming ground loops. lvds outputs output traces and connections must be designed for 50 ? (100 ? differential) characteristic impe dance. keep traces direct and minimize bends wher e possible. avoid crossing ground and power-plane breaks with signal traces. lvcmos outputs output traces and connections must be designed for 50 ? characteristic impedance. unused inputs standard logic inputs (resetn, csb, sclk, sdio, sdo) which will not be operated do not require co nnection to ensure optimal a/d performance. these inputs can be left floating if they are not used. tri-level inputs (napslp, outmode, outfmt) accept a floating input as a valid state, and therefore should be biased according to the desired functionality. definitions analog input bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by fft analysis) is reduced by 3db from its full-scale low-frequency value. this is also referred to as full power bandwidth. aperture delay or sampling delay is the time required after the rise of the clock input for the sa mpling switch to open, at which time the signal is held for conversion. aperture jitter is the rms variation in aperture delay for a set of samples. clock duty cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. differential non-linearity (dnl) is the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) is an alternate method of specifying signal to noise-and-dist ortion ratio (sinad). in db, it is calculated as: enob = (sinad - 1.76)/6.02 gain error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less 2 lsb. it is ty pically expressed in percent. i2e the intersil interleave engine. this highly configurable circuitry performs estimates of offset, gain, and sample time skew mismatches between the core converters, and updates analog adjustments for each to minimize interleave spurs. integral non-linearity (inl) is the maximum deviation of the a/d?s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of lsbs. figure 53. vcm_out output equivalent circuits (continued) vcm avdd 0.535v + C
ISLA110P50 fn7606 rev 2.00 page 32 of 34 july 25, 2011 least significant bit (lsb) is the bit that has the smallest value or weight in a digital word. its value in terms of input voltage is v fs /(2 n -1) where n is the resolution in bits. missing codes are output codes that are skipped and will never appear at the a/d output. thes e codes cannot be reached with any input value. most significant bit (msb) is the bit that has the largest value or weight. pipeline delay is the number of clock cycles between the initiation of a conversion and th e appearance at the output pins of the data. power supply rejection ratio (psrr) is the ratio of the observed magnitude of a spur in the a/d fft, caused by an ac signal superimposed on the power supply voltage. signal to noise-and-distortion (sinad) is the ratio of the rms signal amplitude to the rms sum of all other spectral components below one half the clock frequency, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) is the ratio of the rms signal amplitude to the rms sum of all other spectral components below one-half the sampling frequency, excluding harmonics and dc. snr and sinad are either given in units of db when the power of the fundamental is used as the reference, or dbfs (db to full scale) when the converter?s full-scale input power is used as the reference. spurious-free-dynamic range (sfdr) is the ratio of the rms signal amplitude to the rms value of the largest spurious spectral component. the largest spurious spectral component may or may not be a harmonic.
fn7606 rev 2.00 page 33 of 34 july 25, 2011 ISLA110P50 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2010-2011. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISLA110P50 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 7/6/11 fn7606.2 ? updated intersil trademark statement at bottom of page 1 per directive from legal. ? converted to new datasheet template. ? replaced all occurrences of "fs/ 4 filter" with "notch filter". ? updated over temp note in min max column of spec tables from: unless otherwise noted, parameters with min and/or max limits are 100% production tested at their worst case temperature extreme (+85c). to new standard: "compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." 5/19/10 fn7606.1 ? on page 1: removed clkdiv from key feature list (selectable clock divider: 1 or 2) removed clkdiv pin from ??(was right nexto to clkdivrstp pin) ? on page 3: removed clkdiv pin from ?pin configur ation? diagram, replaced with a dnc pin (pin 16) ? on page 4: removed clkdiv pin from ?pin descriptions? list, added pin 16 to dnc list ? on page 8: under ?cmos inputs? in the ?digital specifications? table, added csb and sclk to the cmos pin list (in parameter column) for i_ih, i_il, v_ih, v_il removed clkdiv reference from ?input current high (outmode, napslp, outfmt) (note 14)? and ?input current low (outmode, napslp, outfmt)? specs ? on page 16: removed text and table describing clkdiv function ? on page 20: removed sentences refe rencing the ?2gsps? block diagram un der the ?clock divider synchronous reset? section as we no longer support this clock distribution block diagram, nor su/hold times to support closing timing at 1ghz input clock ? on page 21: removed sync generation block diagram (f ormer figure 38. synchronization scheme) because we no longer support this architecture ? on page 26: updated ?address 0x71: phase_slip? section to reflect functionality in the clkdiv1 mode. new timing diagram figure 45 to show functionality. removed the ?address 0x72: clock_divide? section an d table for spi address 0x72, clock_divide feature ? on page 29: removed the clock_divide spi register from table 15 under addr 72, replacing with reserved (and indicating which bits must be set to 0) ? on page 31: removed the clkdiv reference in ?unused inputs? section 3/30/10 fn7565.0 initial releas e of production datasheet
ISLA110P50 fn7606 rev 2.00 page 34 of 34 july 25, 2011 package outline drawing l72.10x10c 72 lead quad flat no-lead plastic package (punch qfn) rev 0, 7/07 bottom view side view top view c0.400 x 45 11 1 all around e b l0.450 8.50 ref . 6.00 ref. ( 0 .125) 68x typical recommended land pattern package outline (4x) index area 6 pin 1 4 pin #1 index area 6 r0.200 max all around (4x) y 1 72 0.100 c detail z typ. r0.115 typ. r0.200 r0.200 1 72 exposed pad area x a (4x) (4x) plane seating ( a l l a r o u n d ) z 72 1 0.19~ 0.245 10.00 10.00 9.75 (72x 0.70) (68x 0.50) (72x 0.20) (72x 0.23) 6.00 9.75 10.00 0.85 0.65 0.23 0.50 72x 0.50 0.1 mm b 9.75 10.00 b 0.100 ma c b 0.100 ma c 0.050 mc 0.08 c c 0.25 0.02 detail x detail y 0.15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, to lerance : decimal 0.05; tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metal lized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to jesd-mo220. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: body tolerance: 0.1mm


▲Up To Search▲   

 
Price & Availability of ISLA110P50

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X